2012-11-07 10:55

  CY7C1364CV33 特性
  Registered inputs and outputs for pipelined operation
  256 K × 32 common I/O architecture
  3.3 V core power supply (VDD)
  2.5 V/3.3 V I/O power supply (VDDQ)
  Fast clock-to-output times
  3.5 ns (for 166-MHz device)
  Provide high-performance 3-1-1-1 access rate
  User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
  Separate processor and controller address strobes
  Synchronous self-timed writes
  Asynchronous output enable
  Available in JEDEC-standard lead-free 100-pin TQFP package
  TQFP Available with 3-Chip Enable
  “ZZ” Sleep Mode Option